1. Field of the Invention
The present invention relates generally to a semiconductor memory device and, more particularly, to a sense amplifier fabricated using silicon on insulator (SOI) technology.
2. Description of the Related Art
An increasing number of electronic equipment and electronic-based systems require some form of high-speed memory devices for storing and retrieving information (or xe2x80x9cdataxe2x80x9d). While the types of such memory devices vary widely, semiconductor memory devices are most commonly used in memory applications requiring implementation in a relatively small area. Within this class of semiconductor memory devices, the DRAM (Dynamic Random Access Memory) is one of the more commonly used types.
The DRAM has memory arrays consisting of a number of intersecting row and column lines of individual transistors or memory cells. In a conventional dynamic random access memory (DRAM) device each memory cell, or memory bit, consists of one transistor and one capacitor. A terminal of the transistor is connected to a digit line, or bitline, of the memory device. Another terminal of the transistor is connected to a terminal of the capacitor and the gate terminal of the transistor is connected to a wordline of the memory device. The transistor thus acts as a gate between the digit line and the capacitor.
The second terminal of the capacitor is connected to a voltage rail which carries a voltage, such as Vcc/2. Thus, when the wordline for a particular cell is active, the gate transistor is in a conducting state and the capacitor is connected to the digit line. The capacitor stores a charge that, depending on whether the capacitor is chaged or discharged, represents either a logic high or a logic low value.
Typically, a microcomputer circuit selects (or activates) particular row and column lines to access selected memory cells. xe2x80x9cAccessxe2x80x9d typically refers to reading data from or writing data to selected memory cells. Reading data from the memory cells involves the use of a sense amplifier to detect whether the voltage level stored in the memory cell represents a binary one (logic high) or a binary zero (logic low).
Memory devices are typically constructed with complementary digit lines of equal capcitance. Sense amplifiers are connected between the digit lines and operate to sense the differential voltage across the digit lines. Before a memory cell is selected for access, the complementary digit lines must be equilibrated. Equilibration circuits typically short the complementary digit lines together, resulting in an equilibrate voltage equal to the voltage midpoint between the two equal capacitance and logically opposite digit lines. Conventionally, a DRAM contains one sense amplifier for a designated group (row or column) of memory cells. If the voltage level stored in the memory cell represents a binary zero, one of the digit lines will increase in level, typically to a supply voltage Vcc, and the other digit line will decrease in level, typically to a ground level. If the voltage level stored in the selected memory cell corresponds to a binary one, a change in the opposite direction occurs. Through this complementary operation, the sense amplifier yields a single output signal which is coupled through an output buffer to an output pin of the DRAM device.
FIG. 1 illustrates a sense amplifier 10 of a DRAM device having a first array ARRAY020 and a second array ARRAY122, each of which comprises a plurality of memory cells 21 (shown in ARRAY020). As is generally known in the art, the term sense amplifier includes a collection of circuit elements connected to the digit lines of a DRAM array. This collection typically includes isolation transistors, devices for equilibration and bias, one or more N-sense amplifiers, one or more P-sense amplifiers, and devices connecting selected digit lines to input/output signal lines as will be described below.
As shown in FIG. 1, sense amplifier 10 includes a P-sense amplifier 70 and an N-sense amplifier 80 for sensing charge stored in the selected memory cell of the selected array 20, 22 via a voltage differential on the pair of digit lines D024 and D0* 26. One of the arrays 20, 22 is selected by application of signals ISOa and ISOb to transistors 32a, 32b and 34a, 34b, respectively. Thus, when ISOa is driven to a logic high value and ISOb is driven to a logic low value, transistors 32a and 32b become conductive, i.e., turn on, to connect ARRAY020 to P-sense amplifier 70 and N-sense amplifier 80 while transistors 34a and 34b do not conduct, i.e., turn off, to isolate ARRAY122 from P-sense amplifier 70 and N-sense amplifier 70. When ISOa is driven to a logic low value and ISOb is driven to a logic high value, transistors 34a and 34b turn on to connect ARRAY122 to P-sense amplifier 80 and N-sense amplifier 70 while transistors 32a and 32b turn off to isolate ARRAY020 from P-sense amplifier 80 and N-sense amplifier 70.
Equilibration circuits 50a and 50b are provided to equilibrate the digit lines D024 and D0* 26. Equilibration circuit 50a includes transistor 54 with a first source/drain region coupled to digit line D024, a second source/drain region coupled to digit line D0* 26 and a gate coupled to receive an equilibration signal EQa. Equilibration circuit 50a further includes first and second transistors 56 and 58. Transistor 56 includes a first source/drain region that is coupled to digit line D024, a gate that is coupled to receive the equilibration signal EQa and a second source/drain region that is coupled to receive an equilibration voltage Veq, which, as noted, is typically equal to Vcc/2. Second transistor 58 includes a first source/drain region that is coupled to digit line D0* 26, a gate that is coupled to receive the equilibration signal EQa and a second source/drain region that is coupled to the equilibration voltage Veq. When the signal EQa is at a high logic level, equilibration circuit 50a effectively shorts digit line D024 to digit line D0* 26 such that both lines are equilibrated to the voltage Veq. Equilibration circuit 50b is constructed in a similar manner to equilibration circuit 50a and operates when the EQb signal is at a high logic level.
When P-sense amplifier 70 and N-sense amplifier 80 have sensed the differential voltage across the digit lines D024 and D0* 26 (as described below), a signal representing the charge stored in the accessed memory cell is output from the DRAM device on the input/output (I/O) lines I/O 36 and I/O* 38 by connecting the I/O lines I/O 36 and I/O* 38 to the digit lines D024 and D0* 26, respectively. A column select (CSEL) signal is applied to transistors 40, 42 to turn them on and connect the digit lines D024 and D0* 26 to the I/O lines I/O 36 and I/O* 38.
The operation of the P-sense amplifier 80 and N-sense amplifier 70 is as follows. These amplifiers work together to detect the access signal voltage and drive the digit lines D024 and D0* 26 to Vcc and ground accordingly. As shown in FIG. 1, the N-sense amplifier 80 consists of cross-coupled NMOS transistors 82, 84 and drives the low potential digit line to ground. Similarly, the P-sense amplifier 70 consists of cross-coupled PMOS transistors 72, 74 and drives the high potential digit line to Vcc. The NMOS pair 82, 84 or N-sense-amp common node is labeled RNL*. Similarly, the P-sense-amp 70 common node is labeled ACT (for ACTive pull-up). Initially, RNL* is biased to Vcc/2 and ACT is biased to ground. Since the digit line pair D024 and D0* 26 are both initially at Vcc/2 volts, the N-sense-amp transistors 82, 84 remain off due to zero Vgs potential. Similarly, both P-sense-amp transistors 72, 74 remain off due to their negative Vgs potential. As discussed in the preceding paragraph, a signal voltage develops between the digit line pair 24, 26 when the memory cell access occurs. While one digit line contains charge from the cell access, the other digit line serves as a reference for the sensing operation. The sense amplifier firing generally occurs sequentially rather than concurrently. The N-sense-amp 80 fires first and the P-sense-amp 70 second. Dropping the RNL* signal toward ground will fire the N-sense-amp 80. As the voltage between RNL* and the digit lines approaches the transistor threshold voltage Vt, the NMOS transistor whose gate connection is to the higher voltage digit line will begin to conduct. Conduction results in the discharge of the low voltage digit line toward the RNL* voltage. Ultimately, RNL* will reach ground, bringing the digit line with it. Note that the other NMOS transistor will not conduct since its gate voltage derives from the low voltage digit line, which is discharging toward ground.
Shortly after the N-sense-amp 80 fires, ACT will be driven toward Vcc. This activates the P-sense-amp 70 that operates in a complementary fashion to the N-sense-amp 80. With the low voltage digit line approaching ground, a strong signal exists to drive the appropriate PMOS transistor into conduction. This will charge the high voltage digit line toward ACT, ultimately reaching Vcc. Since the memory bit transistor remains on during sensing, the memory bit capacitor will charge to the RNL* or ACT voltage level. The voltage, and hence charge, which the memory bit capacitor held prior to accessing will restore a full level, i.e., Vcc for a logic one and GND for a logic zero.
There has been renewed interest in the fabrication of DRAMs using Silicon on Insulator (SOI) technology. In an SOI device, an insulating layer is provided between the transistors of the DRAM and the substrate. While this technology is currently more expensive in terms of manufacturing costs, the are some compelling benefits. Transistors manufactured within an SOI device tend to be faster due to significantly reduced junction capacitance. Further, these devices are immune to latch-up, and have significantly reduced software error rates.
There are, however, certain problems associated with SOI devices. In an SOI device, if body contacts are not provided, the body of the individual transistors are no longer tied to the bulk substrate. Variations in body potential can cause variations in the threshold voltage Vt from device to device and over time based on the previous potentials on the device""s source/drain/gate terminals. Variations in the threshold voltage Vt can alter speed paths within a device, or make balanced circuits difficult to produce.
In a DRAM, one particularly sensitive circuit is the sense amplifier, such as sense amplifier 10 illustrated in FIG. 1. As previously described, the sense amplifier 10 is designed to amplify small signal differential on the digit lines D024 and D0* 26. In order to properly detect these small differentials, the sense amplifier 10 must be balanced. For SOI technology, the cross coupled NMOS transistors 82, 84 should have matching threshold voltages Vt. To ensure that the NMOS transistors 82, 84 have matching threshold voltages Vt, the body nodes of the two transistors 82, 84 must be contacted in some way and either tied together or to a common potential. It has been suggested that the NMOS transistor bodies be tied to a high potential to reduce the threshold voltage Vt of the transistors, thereby aiding in the fast sensing of the signals on the digit lines D024 and D0* 26. However, low threshold voltages Vt for the transistors in the sense amplifier 10 will lead to an increased leakage current through the sense amplifier 10 whenever the sense amplifier 10 is active, which in turn will degrade the operation of the memory device.
Thus, there exists a need for sense amplifier circuitry that reduces the leakage current through the sense amplifier circuitry while the array is active, while controlling the body voltage of the sense amplifier transistors to improve performance of the sense amplifier circuitry.
The present invention alleviates the problems associated with the prior art and provides a DRAM sense amplifier that reduces the leakage current through the sense amplifier circuitry while the array is active, while controlling the body voltage of the sense amplifier transistors to improve performance of the sense amplifier circuitry.
In accordance with the present invention, the body nodes of the sense amplifier transistors are pre-charged to a voltage potential, such as for example Vcc/2. The body nodes are disconnected from the pre-charge voltage while the sense amplifier is enabled, i.e., during an access operation, but the threshold voltage Vt of the sense amplifier transistors will be lower during sensing due to the pre-charge level. As the body potential drops during sensing, the threshold voltage Vt will increase, thereby reducing the leakage current that flows through the sense amplifier while the digit lines are electrically separated.
These and other advantages and features of the invention will become more readily apparent from the following detailed description of the invention which is provided in connection with the accompanying drawings.